1. Technical Field of the Invention
This invention relates generally to integrated circuits and more particularly to frequency synthesizers.
2. Description of Related Art
The concept of converting one clock rate to another is well known in the art and is generally referred to as frequency synthesis. One commonly known frequency synthesizer is a phase locked loop (PLL). As is known, a typical implementation of a PLL includes a phase and frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a feedback divider. The phase and frequency detector generates an up signal or a down signal based on a phase and/or frequency difference between a reference clock and a feedback clock that is produced by the feedback divider. The phase and frequency detector generates the up signal when the phase and/or frequency of the reference clock leads the phase and/or frequency of the feedback clock, which results when the desired output oscillation is too slow. The phase and frequency detection module generates the down signal when the phase and/or frequency of the reference clock lags the phase and/or frequency of the feedback clock, which results when the desired output oscillation is too fast.
The charge pump converts the up signal and down signal into a current. The loop filter converts the current produced by the charge pump into a control voltage. The voltage controlled oscillator produces the output oscillation (i.e., the desired output clock) based on the control voltage. The feedback divider divides the output oscillation by a divider value to produce the feedback clock. For example, if the reference oscillation is 20 MHz and the desired output oscillation is 110 MHz, the divider value is 5.5.
Such a PLL includes analog circuitry to implement one or more of its components. As is known, analog circuits are susceptible to noise generated by digital circuits. In lower rate applications, i.e., applications that do not push the processing limits of the integrated circuit manufacturing process (e.g., a few hundred MHz for 0.13 micron CMOS technology), the digital noise does not significantly affect the performance of the analog components. However, as the rate of operations increase, the digital noise becomes a more significant issue for the analog components and adversely affects their performance.
Recently, a digital frequency synthesizer has been developed for high rate applications. FIG. 1 illustrates a schematic block diagram of such a digital frequency synthesizer that includes an edge triggered set/reset flip-flop module, a digital delay line, a multiplexer, an M counter, a comparator, and a D counter. In operation, the digital delay line oscillates at a rate of (M/D) times the rate of an input clock (CLK in). For example, if the input clock is 20 MHz, M=7 and D=3, the rate of the output clock (CLK out) is 7/3 times 20 MHz, which equals 46.67 MHz. The rate of the digital delay line can be adjusted via the oscillation rate control module to ensure that the rate is near the desired rate.
To achieve phase and frequency lock between the input clock and the output clock, edge triggered set/reset flip-flop modules sets the input of the delay line at the earlier of D cycles of the input clock or M cycles of the output clock. Further, based on a phase difference between the occurrence of D cycles of the input clock and M cycles of the output clock, the comparator increments or decrements a tap selection of the digital delay line to reduce the phase error between the two clock cycle counts.
While the digital frequency synthesizer of FIG. 1 is a fully digital implementation, thus eliminating the issues with analog frequency synthesizers, a small amount of jitter is produced. FIG. 2 illustrates the generation of such jitter. As shown, for every D cycles of the input clock (e.g., 3), the digital delay line is set causing the output clock to commence in a new cycle in step with a new cycle of the input clock. This forcing of a new cycle, if the output clock is not exactly M/D times the input clock, will cause jitter. In current high rate applications, this small amount of jitter has minimal adverse affects on the operation of the integrated circuit. However, for ultra high rate applications, (e.g., rates approaching the giga Hertz range and above), the small amount of jitter may have some adverse affects on the performance of an integrated circuit.
Therefore, a need exists for a low jitter digital frequency synthesizer and method of controlling such a synthesizer.